In recent years, a digital modulation system has been practically used in a mobile communication system, and circuit integration of a quadrature modulator constituting a modulator section for performing multi-value digital modulation such as QPSK (Quaternary Phase Shift Keying) has been increasing in importance.
FIG. 15 is a block diagram illustrating a general construction of a prior art quadrature modulator. In the figure, reference numeral 150 designates a quadrature modulator. The quadrature modulator 150 includes a 0.degree./90.degree. phase shifter 1 which, connected to a signal input terminal (IN) 10, separates an input carrier wave (hereinafter referred to simply as carrier) into two sinusoidal signals having a phase difference of 90.degree. from each other, double-balanced mixers 2 and 3 performing modulation by mixing base band signals on the output carrier waves output from the 0.degree./90.degree. phase shifter, and an in-phase synthesizer 4 which synthesizes modulated signals of the double-balanced mixers 2 and 3 and outputs the signals to an output terminal (OUT) 20. The double-balanced mixer 2 is for the I (In-phase) channel and the double-balanced mixer 3 is for the Q (Quadrature-phase) channel. A base band signal (I.sub.BB) at the I-channel is input from a base band signal input terminal 5 and a base band signal (Q.sub.BB) at the Q-channel is input from a base band signal input terminal 6.
In such a quadrature modulator, in order to realize superior modulation, it is necessary to obtain a modulated wave spectrum including fewer spurious components such as image components or carrier leakage. Thus, in order to sufficiently suppress the image component relative to the modulation signal component, the orthogonality of two carriers which are input to the two double-balanced mixers 2 and 3 is important, and the precision of orthogonality of the carriers in the 0.degree./90.degree. phase shifter 1, i.e., how precisely the carrier is separated into two sinusoidal signals having a phase difference of 90.degree. from each other, is important. In addition, amplitude errors in complementary carriers which are input to the respective double-balanced mixers 2 and 3 also cause spurious components such as image components or carrier leakage, and therefore, it is also important to decrease these amplitude errors so as to obtain a modulated wave spectrum including fewer spurious components. Consequently, in order to carry out circuit integration of a quadrature modulator which is superior in its modulation characteristics, how the complementary carriers which are superior in the balancing, i.e., which includes fewer amplitude errors are input to the double balanced mixers by including a 0.degree./90.degree. phase shifter which is superior in the orthogonality of its output carriers and is appropriate for circuit integration, is important, and this determines the performance of the quadrature modulator integrated circuit and the yield thereof.
A description is given of an example and characteristics of a 0.degree./90.degree. phase shifter which is conventionally proposed.
FIG. 16 shows a circuit diagram of a prior art 0.degree./90.degree. phase shifter which is constructed with a high pass filter and a low pass filter each comprising inductors (L) and capacitors (C). In the figure, reference numeral 160 designates a 0.degree./90.degree. phase shifter. This 0.degree./90.degree. phase shifter 160 includes an in-phase power separating circuit 7a connected to a signal input terminal (IN) 10, and a low pass filter 7b and a high pass filter 7c which separates the output of the in-phase power separating circuit 7a to two output signals having a phase difference of 90.degree. from each other and outputs those output signals to the signal output terminals (OUT1) 20a and (OUT2) 20b, respectively. The low pass filter 7b includes inductors L1 and L2 serially connected between the in-phase power separating circuit 7a and the output terminal 20a and a capacitor C3 connected between the node of two inductors L1 and L2 and the ground. The high pass filter 7c includes capacitors C1 and C2 serially connected between the in-phase power separating circuit 7a and the output terminal 20b and an inductor L3 connected between the node of two capacitors C1 and C2 and the ground.
In this 0.degree./90.degree. phase shifter 160, it is possible to take out signals having a 90.degree. phase difference from two signal output terminals 20a (OUT1) and 20b (OUT2) by selecting values of three inductors L1 to L3 and three capacitors C1 to C3 appropriately. While this 0.degree./90.degree. phase shifter has low insertion loss or the like, when it is operable at a submicrowave band, for example, 800 MHz band, or in a 1.9 GHz band used in digital portable telephone or digital codeless telephone, its circuit integration and miniaturization are difficult due to the inductors L1 to L3 occupying a large area.
FIGS. 17(a) and 17(b) show a construction of a 1/4 wavelength coupling directional coupler, where FIG. 17(a) is a top view thereof, and FIG. 17(b) is a sectional view thereof along line 17b--17b of FIG. 17(a). In the figure, reference numeral 170 designates a 1/4 wavelength coupling directional coupler, which includes coupling line conductors 9a, 9b arranged on the top surface of a substrate 8 comprising alumina or the like and a ground conductor 9c arranged on the under surface of the substrate 8. These two coupling line conductors 9a, 9b and ground conductor 9c constitute microstrip lines. Reference numerals 11a to 11d in the figure designate input or output ports.
In this 1/4 wavelength coupling directional coupler 170, when the three ports 11a, 11c, and 11d are terminated with 50.OMEGA. and the port 11b receives a driving source having an internal resistance 50.OMEGA., no output signal appears at the port 11c and output signals having a 90.degree. phase difference appear at the ports 11a, 11d, respectively. Consequently, this 1/4 wavelength coupling directional coupler can be operated as a 0.degree./90.degree. phase shifter. In this 1/4 wavelength side coupling directional coupler 170, however, because coupling line conductors 9a, 9b are required to have a conductor length of 1/4 wavelength, respectively, when it is operable at submicrowave band, for example, 800 MHz band, or in a 1.9 GHz band used in digital portable telephones or digital cordless telephones, conductor lengths of coupling line conductors 9a, 9b are longer and the grounded areas are increased, thereby resulting in difficulties in circuit integration and miniaturization.
FIG. 18(a) and 18(b) illustrates a construction of a 1/4 wavelength branch line type directional coupler, where FIG. 18(a) is a top view thereof, FIG. 18(b) is a sectional view thereof along line 18b--18b of FIG. 18(a), and FIG. 18(c) is a sectional view along line 18c--18c of FIG. 18(a). In the figure, reference numeral 180 designates a 1/4 wavelength branch line type directional coupler, which includes branch line conductor 12a arranged on the top surface of substrate 8 comprising alumina or the like and ground conductor 12b. These branch line conductor 12a and ground conductor 12b constitute microstrip lines. Reference numerals 13a to 13d designate input or output ports.
In this 1/4 wavelength branch line type directional coupler, for example, when the three ports 13a, 13c and 13d are terminated with 50.OMEGA. and the port 13b receives a driving source of internal resistance 50.OMEGA., no output signals appear at the port 13a and output signals having a 90.degree. phase difference appear at the port 13c, 13d, respectively. Consequently, this 1/4 wavelength branch line type directional coupler can be operated as a 0.degree./90.degree. phase shifter. However, because conductor lengths P1 to P2, P2 to P3, P3 to P4 and P4 to P1 at the branch line conductor 12a are required to be 1/4 wavelengths, when it is operable at submicrowave band such as 800 MHz band or in a 1.9 GHz band which are used in digital portable telephones or digital cordless telephones, the conductor lengths of the branch line conductors 12a are longer and the grounded area is larger, thereby resulting in difficulties in circuit integration and miniaturization, similarly to the 1/4 wavelength side coupling directional coupler 170 illustrated in FIG. 17(a).
Contrary to the conventional 0.degree./90.degree. phase shifters illustrated in FIGS. 16 to 18 which are not appropriate for circuit integration and miniaturization, there is a 90.degree. phase shifter illustrated in FIG. 19 and FIG. 21 without inductors or 1/4 wavelength lines, which is appropriate for circuit integration and which can be constituted by only resistors and capacitors, or by only resistors, capacitors and transistors, which require no wide chip areas, respectively.
FIG. 19 shows a circuit diagram illustrating an example of a 0.degree./90.degree. phase shifter having such a circuit construction. In the figure, reference numeral 190 designates a 0.degree./90.degree. phase shifter. This 0.degree./90.degree. phase shifter includes a differential amplifier circuit 15 which is inserted between a power supply terminal (V.sub.DD) 17 and the ground and to which the input carriers are input from a positive phase signal input terminal (IN1) 10a and a negative phase signal input terminal (IN2) 10b, two source followers 16a, 16b connected at the later stage of the differential amplifier circuit 15, and a signal separating circuit 18 of an all band pass type circuit which separates the outputs of these two source followers 16a, 16b into two carriers comprising sinusoidal signals having a 90.degree. phase difference and outputs them to the output signal terminals (OUT1) 20a and (OUT2) 20b, respectively.
In the differential amplifier circuit 15, reference characters J11 to J13 designate FETs and reference characters R11 to R13 designate resistors. The gates of FETs J11, J12 are connected to positive phase signal input terminal (IN1) 10a and negative phase signal input terminal (IN2) 10b, respectively, the sources of FETs J11, J12 are connected to the drain of FET J13, and the drains of FETs J11, J12 are connected to power supply terminal V.sub.DD 17 via two resistors R11 and R12, respectively. The source of FET J13 is grounded via resistor R13, and the gate thereof is connected to a constant-current source bias terminal Vcs 14.
In the source follower 16a, reference characters J14, J15 designate FETs, reference character R14 designates a resistor, and the gate of FET J14 is connected to the connection node between resistor R11 and FET J11, the drain thereof is connected to power supply terminal V.sub.DD 17, and the source thereof is connected to the drain of FET J15. The source of FET J15 is grounded via resistor R14, and the gate thereof is connected to the constant-current source bias terminal Vcs 14.
In the source follower 16b, reference characters J16, J17 designate FETs, reference character R15 designates a resistor, and the gate of FET J16 is connected to the connection node between resistor R12 and FET J12, the drain thereof is connected to power supply terminal V.sub.DD 17, and the source thereof is connected to the drain of FET J17. The source of FET J17 is grounded via resistor R15, and the gate thereof is connected to the constant-current source bias terminal Vcs 14.
In the signal separating circuit 18, reference characters Ra, Rb designate resistors, and reference characters Ca, Cb designate capacitors. Resistor Ra and capacitor Ca, serially connected, and resistor Rb and capacitor Cb, serially connected, are connected in parallel with each other between the connection node n11 between FET J14 and FET J15 and the connection node n12 between FET J16 and FET J17.
The differential amplifier circuit 15 is provided as means for inputting signals of reverse phases to each other to the gates of FETs J14, J16 of source followers 16a, 16b, respectively. The input signals which are input to the positive phase signal input terminal (IN1) 10a and the negative phase signal input terminal (IN2) 10b, respectively, are not necessarily required to be of reverse phases. Either of the two signals can be a reference voltage.
Reference characters V1, V2 in the figure designate voltages at the connection node n11 between the FET J14 and the FET J15, and the connection node n12 between the FET J16 and the FET J17, respectively.
FIG. 20 is a diagram illustrating the voltage vector V1 at the connection node n11 between the FET J14 and the FET J15, the voltage vector V2 (=-V1) at the connection node n12 between the FET J16 and the FET J17, and output voltage vectors Vout1, Vout2, when the values of resistors Ra, Rb and capacitors Ca, Cb constituting the signal separating circuit in the 0.degree./90.degree. phase shifter in FIG. 19 are selected so that the output voltages Vout1 and Vout2 are orthogonal to each other at the design frequency f.sub.0. Reference characters Ia, Ib in the figure designate a current flowing through the connection node n.sub.a between resistor Ra and capacitor Ca, and a current flowing through the connection node n.sub.b between resistor Rb and capacitor Cb, respectively. In addition, this figure shows a vector diagram, when the angle .PHI.1 produced by the voltage vectors V1 and Ia/j.omega.Ca (j is the imaginary unit, .omega. is angular frequency) and the angle .PHI.2 produced by the voltage vectors V2 and RbIb are both set to 22.5.degree., .DELTA..PHI. in the figure represents a phase difference between the output voltages Vout1 and Vout2.
It is found from this figure that the amplitudes of the output voltages Vout1 and Vout2 are equal to the amplitudes of V1 and V2 over a wide band, because the signal separating circuit 18 is an all band pass type circuit. However, because the currents Ia and Ib generating the output voltages Vout1 and Vout2 of the signal separating circuit 18, respectively, are provided separately, the frequency band that can maintain a phase difference of 90.degree. cannot be made so wide, and when there arise element variations in the resistors Ra and Rb and the capacitors Ca and Cb during circuit integration (i.e., when the values of the resistors Ra, Rb and the capacitors Ca, Cb fall outside the design values during manufacturing), it is impossible to separate signals exactly into signals of 0.degree. and 90.degree., respectively, thereby resulting in low precision in orthogonality as a function of variations in element characteristics.
FIG. 21 shows a circuit diagram illustrating a 0.degree./90.degree. phase shifter including a signal separating circuit comprising a differentiating circuit and an integrating circuit. In the figure, reference character 210 designates a 0.degree./90.degree. phase shifter. This 0.degree./90.degree. phase shifter 210 includes two source followers 16c and 16d to which the input carrier from a signal input terminal (IN) 10c is input and which are connected in parallel between power supply terminal V.sub.DD 17 and the ground, and a signal separating circuit 19 which separates the outputs of these two source followers 16c and 16d into two signals having a 90.degree. phase difference, to output them to the signal output terminals (OUT1) 20a and (OUT2) 20b, respectively. This signal separating circuit 19 comprises the differentiating circuit 19a and the integrating circuit 19b. In the source follower 16c, reference characters J21 and J22 designate FETs, reference character R21 designate a resistor, the gate of the FET J21 is connected to the input terminal (IN) 10c, the drain thereof is connected to the power supply terminal V.sub.DD 17, and the source thereof is connected to the drain of the FET J22. The source of the FET J22 is grounded via the resistor R21, and the gate thereof is connected to the constant-current source bias terminal Vcs 14.
In the source follower 16d, reference characters J23 and J24 designate FETs, reference character R22 designate a resistor, and the gate of the FET J23 is connected to the input terminal (IN) 10c, the drain thereof is connected to the power supply terminal V.sub.DD 17, and the source thereof is connected to the drain of the FET J24.
The source of the FET J24 is grounded via the resistor R22, and the gate thereof is connected to the constant-current source bias terminal Vcs 14.
In the differentiating circuit 19a, reference character Ra designates a resistor and reference character Ca designates a capacitor. The resistor Ra and the capacitor Ca, serially connected to each other, are inserted between the connection node n21 of the FETs J21 and J22 and the ground, and the connection node n.sub.a between the resistor Ra and the capacitor Ca is connected to the output signal terminal (OUT1) 20a.
In the integrating circuit 19b, reference character Rb designates a resistor and reference character Cb designates a capacitor. The resistor Rb and the capacitor Cb, serially connected, are inserted between the connection node n23 of FET J23 and FET J24 and the ground, and the connection node n.sub.b between resistor Rb and capacitor Cb is connected to the output terminal (OUT2) 20b.
Reference characters V1 and V2 in the figure designate voltages at the connection node n21 between FET J21 and FET J22 and at the connection node n23 between FET J23 and FET J24, respectively, and reference characters Vout1 and Vout2 designate output voltages of signal output terminals (OUT1) 20a and (OUT2) 20b, respectively.
FIG. 22 is a diagram showing vectors V1, V2 (=V1), Vout1 and Vout2, when the values of the resistors Ra, Rb and the capacitors Ca, Cb of the differentiating circuit 19a and the integrating circuit 19b are set so as to satisfy the following: EQU Ra=Rb=R, Ca=Cb=C, f.sub.0 =1/(2.pi.RC) (1)
at the design frequency f.sub.0, supposing that the output impedances of the two source followers 16a, 16b in the 0.degree./90.degree. phase shifter in FIG. 21 are sufficiently low. FIG. 22(a) is a vector diagram at frequency f=f.sub.0, and FIG. 22(b) illustrates a vector diagram at a frequency other than f=f.sub.0. In the figure, reference characters Ia, Ib designate a current flowing through the connection node n.sub.a between the resistor Ra and the capacitor Ca, and a current flowing through the connection node n.sub.b between the resistor Rb and the capacitor Cb, respectively. Reference character .theta.1 designates a phase difference between V1 and Vout1, and reference character .theta.2 designates a phase difference between V1 and Vout2. In addition, reference character O designates a node at the ground potential, and reference characters A, B, P designate terminuses of the vectors, respectively.
In FIG. 22(a), both .DELTA.OAP and .DELTA.OBP are right-angled isosceles triangles which are congruent with each other. Consequently, because at frequency f=f.sub.0 the differentiating circuit 19a advances the phase of the input V1 by 45.degree. and the integrating circuit 19b retards the phase of the input V2 by 45.degree., it is found that the phase difference between the outputs Vout1 and Vout2 (.theta.1+.theta.2) is 90.degree.. At this time, however, the amplitudes of the outputs Vout1 and Vout2 are reduced to lower values than the amplitude of the input V1 (=V2) due to the high pass characteristic of the differentiating circuit 19a and the low pass characteristic of the integrating circuit 19b.
In FIG. 22(b), the following formulae stand independently of the frequency from the relation of the formula (1): EQU OA=BP, AP=OB and .angle.OAP=.angle.OBP=90.degree..
Consequently, EQU .angle.AOP=.angle.BPO=.theta.1, .angle.BOP=.angle.APO=.theta.2, and .angle.OAP=.angle.OBP=90.degree..
When it is considered that the sum of the three angles of a triangle is 180.degree., it follows that, EQU .angle.AOP+.angle.BOP=.theta.1+.theta.2=90.degree.,
i.e., that the phase difference of the outputs Vout1 and Vout2 (.theta.1+.theta.2) is still 90.degree. at frequencies other than f=f.sub.0.
However, the amplitudes of Vout1 and Vout2 are different from each other.
FIG. 23 is a diagram showing vectors V1, V2 (=V1), Vout1 and Vout2, when the resistance values of the resistors Ra, Rb (=Ra) constituting a different circuit 19a and an integrating circuit 19b in the 0.degree./90.degree. phase shifter illustrated in FIG. 21 are a little larger than the design value R, or when the capacitance values of the capacitors Ca, Cb (=Ca) constituting a differentiating circuit 19a and an integrating circuit 19b in the 0.degree./90.degree. phase shifter illustrated in FIG. 21 are a little larger than the design value C. Reference character .theta.1 in the figure designates a phase difference between V1 and Vout1, and reference character .theta.2 designates a phase difference between V1 and Vout2.
From this figure, it is found that when the circuit elements, i.e., the resistors Ra, Rb and the capacitors Ca, Cb vary, the angle .theta.1 produced by Vout1 and V1 is small, the angle .theta.2 produced by Vout2 and V2 is large, and the amplitudes of Vout1 and Vout2 are different from each other at frequency f=f.sub.0, while the sum of the both phase differences (.theta.1+.theta.2) is still kept at 90.degree..
FIG. 24 shows a diagram illustrating amplitude characteristics of the output signals Vout1 and Vout2 as a function of input frequency of the 0.degree./90.degree. phase shifter shown in FIG. 21. From this figure, it is found that the frequency at which the amplitudes of the output signals Vout1 and Vout2 become equal to each other is only f=f.sub.0 due to the high pass characteristic of the differentiating circuit 19a and the low pass characteristic of the integrating circuit 19b.
As described above, a 0.degree./90.degree. phase shifter including a signal separating circuit comprising a differentiating circuit and an integrating circuit, can be structured with only resistors and capacitors, or resistors, capacitors and transistors, which are appropriate for circuit integration and miniaturization. Further, the operation characteristics of the phase shifter can maintain orthogonality over a wide band as well as a high degree of the orthogonality as a function of element variations. As is seen from the frequency characteristics in FIG. 24, however, the amplitude error of the carrier at other than the central frequency f.sub.0 is large, and when a quadrature modulator using this 0.degree./90.degree. phase shifter is employed, the carrier waves with large amplitude errors are directly input to double balanced mixers, thereby still generating spurious components, not resulting in preferable modulator characteristics.